Course Number : SI-2026-30
Eligible students to participate : B.Tech. 3rd year
Prerequisites : • Basic knowledge of Digital Electronics Circuit, • Basic knowledge on Verilog
Resource person(s) :
  • Silicon Faculty:
  • Prof. Debasish Nayak
  • Industry Expert:
  • Expert from Scaledge India 
Duration of the Course : 3 weeks – 100 hrs(Theory : 70 hrs, Hands-on :30 hrs)
Course Outcome :
  • After completing the course, the students will be able to design digital systems using System Verilog HDL.
  • They will learn how to perform digital system verification using System Verilog.
  • Students will have an exposure to the best industry practice in the domain of System Verilog
Course Content :

Essential concepts of Verilog

  • Introduction to Verilog
  • Various Modeling Technique
  • Combinational logic
  • Flip-flop
  • Timing Analysis
  • Design of Sequential Circuit
  • Registers /Counters
  • Blocking / Non-blocking style
  • Fork-Join / Begin-End
  • FSM based design: Sequence Detector

Concepts of System Verilog

  • Object oriented programming
  • Data types
  • Operators
  • Arrays
  • Inter process synchronization.
  • More scheduling regions
  • Interface
  • Program
  • Clocking block
  • Modport Fork join (multiple variations)
  • Constraints
  • Randomization
  • Assertions
  • Functional coverage

Project:

  • Verification of memory block using System Verilog
  • Advanced Peripheral Bus protocol using System Verilog
Details...
Methodology of Course Delivery :
  • Classroom Teaching ( Offline)
  • Hands-on Lab practices
Batch Size : 40
Course Schedule : 25th May 2026-4th July 2026
Course Fees : 6500 INR
Residence Fee (optional) : 0 INR

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