Silicon Faculty:

• Prof. Joy Chowdhury
• Prof. DhananjayaTripathy

Industry & External Expert:

• Mr. Mukesh Shukla, VLSI Pro

Upon successful completion of this course, students will:

• Develop a strong foundation in the Digital VLSI Design Flow, including RTL modeling, functional verification, and synthesis.

• Gain proficiency in writing structured and synthesizable Verilog HDL for combinational and sequential digital systems.

• Understand hierarchical and modular hardware design, enabling systematic development of digital building blocks.

• Progressively design and implement key architectural components of a Simplified RISC-V Processor, including ALU, Register File, Memory Subsystem, and Control Unit.

• Understand Instruction Execution Cycle, Datapath and Control Path integration, and processor-level system design concepts.

• Implement and validate the complete design on an FPGA platform, bridging simulation with real hardware realization.

• Build a strong technical foundation for careers in Processor Design, VLSI, and FPGA-based System Development.

RTL-to-Chip: Practical Digital System Design Case Study

Module 1: RTL Fundamentals and Digital Block Design

Module 2: Memory and Register Subsystem

Module 3: FSM and Control Path Design

Module 4: Processor Architecture and Integration

Module 5: Verification and Implementation

• Classroom Teaching ( Offline)
• Hands-on Lab sessions